1. Field of the Invention
The present invention relates to a differential amplifier circuit and a load driving circuit including the differential amplifier circuit. More specifically, the present invention relates to a differential amplifier circuit having a differential amplifier circuit section which amplifies a difference voltage between a non-inverting input node and an inverting input node, and an output buffer circuit, which outputs a signal based on the output of the differential amplifier circuit section.
2. Background Art
FIG. 9 shows a structure of a conventional differential amplifier circuit. In FIG. 9, reference numeral 1 denotes a high potential power supply node to which a positive power supply potential is applied; 2, a low potential power supply node at a ground potential; 5, an inverting input terminal to which a first input signal is input; 6, a non-inverting input terminal to which a second input signal is input; and 7, an output terminal. Reference numeral 10 denotes a differential amplifier circuit driven by potentials that are applied to the high potential and low potential power supply nodes 1 and 2. The differential amplifier circuit 10 amplifies a difference voltage between first and second input signals that are input to the inverting and non-inverting input terminals 5 and 6, respectively, and outputs an amplified difference voltage to the output terminal 7.
However, in the above-configured differential amplifier circuit, the dynamic range of the output signal depends on the potentials that are applied to the high potential and low potential power supply nodes 1 and 2.
In general, potential of 5 V or 12 V is used in a semiconductor integrated circuit device that incorporates the differential amplifier circuit. For example, where a potential of 5 V is applied to the high potential power supply node 1, the dynamic range of the output of the differential amplifier circuit 10 is about 0 V to about 5 V (correctly, it is narrower than this range because of the influence of a transistor at the output stage of the differential amplifier circuit 10). Where a potential of 12 V is applied to the high potential power supply node 1, the dynamic range of the output of the differential amplifier circuit 10 is about 0 V to about 12 V (correctly, it is narrower than this range because of the influence of a transistor at the output stage of the differential amplifier circuit 10).
Where a potential of 5 V is applied to the high potential power supply node 1 in the differential amplifier circuit 10, the upper potential limit of the output is not sufficiently close to 5 V.
Further, even where the output needs to be 5 V or more but need not be as high as 12 V, a potential of 12 V is applied to the high potential power supply node 1. In this case, the power consumption of the entire differential amplifier circuit is unnecessarily large.